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AL Tech 8CH Manual de usuario Pagina 10

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LTC2424/LTC2428
PIN FUNCTIONS
UU
U
CSADC (Pin 23): ADC Chip Select Input. A low on this pin
enables the SDO digital output and following each conver-
sion, the ADC automatically enters the Sleep mode and
remains in a low power state as long as CSADC is high. If
CSADC is low during the sleep state, the device draws
normal power. A high on this pin also disables the SDO
digital output. A low-to-high transition on CSADC during
the Data Output state aborts the data transfer and starts a
new conversion. For normal operation, drive this pin in
parallel with CSMUX.
SDO (Pin 24): Three-State Digital Output. During the data
output period this pin is used for serial data output. When
the chip select CSADC is high (CSADC = V
CC
), the SDO pin
is in a high impedance state. During the Conversion and
Sleep periods, this pin can be used as a conversion status
output. The conversion status can be observed by pulling
CSADC low.
SCK (Pin 25): Shift Clock for Data Out. This clock synchro-
nizes the serial data transfer of the ADC data output. Data
is shifted out of SDO on the falling edge of SCK. For normal
operation, drive this pin in parallel with CLK.
F
O
(Pin 26): Digital input which controls the ADC’s notch
frequencies and conversion time. When the F
O
pin is
connected to V
CC
(F
O
= V
CC
), the converter uses its internal
oscillator and the digital filter first null is located at 50Hz.
When the F
O
pin is connected to GND (F
O
= OV), the
converter uses its internal oscillator and the digital filter
first null is located at 60Hz. When F
O
is driven by an
external clock signal with a frequency f
EOSC
, the converter
uses this signal as its clock and the digital filter first null is
located at a frequency f
EOSC
/2560. The resulting output
word rate is f
EOSC
/20510.
AUTOCALIBRATION
AND CONTROL
DECIMATING FIR
INTERNAL
OSCILLATOR
SERIAL
INTERFACE
CHANNEL
SELECT
ADC
DAC
∑
∫∫∫
GND
8-CHANNEL MUX
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
V
CC
SDO
SCK
FS
SET
ZS
SET
CSADC
F
O
(INT/EXT)
24248 BD
CSMUX
D
IN
CLK
FU CTIO AL BLOCK DIAGRA
UU
W
TEST CIRCUITS
3.4k
SDO
24248 TC01
Hi-Z TO V
OH
V
OL
TO V
OH
V
OH
TO Hi-Z
C
LOAD
= 20pF
3.4k
SDO
24248 TC02
Hi-Z TO V
OL
V
OH
TO V
OL
V
OL
TO Hi-Z
C
LOAD
= 20pF
V
CC
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