13
LTC2424/LTC2428
APPLICATIONS INFORMATION
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The LTC2424/LTC2428 can be interchanged with the
LTC2404/LTC2408. The two devices are designed to allow
the user to incorporate either device in the same design as
long as ZS
SET
(Pin 5) of the LTC2424/LTC2428 is tied to
ground. While the LTC2424/LTC2428 output word lengths
are 24 bits (as opposed to the 32-bit output of the LTC2404/
LTC2408), their output clock timing can be identical to the
LTC2404/LTC2408. As shown in Figure 3, the LTC2424/
LTC2428 data output is concluded on the falling edge of the
24th serial clock (SCK). In order to maintain drop-in com-
patibility with the LTC2404/LTC2408, it is possible to clock
the LTC2424/LTC2428 with an additional 8 serial clock
pulses. This results in 8 additional output bits which are logic
HIGH.
Bit 23 (first output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 22 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 21 (third output bit) is the conversion result sign indi-
cator (SIG). If V
IN
is >0, this bit is HIGH. If V
IN
is <0, this
bit is LOW. The sign bit changes state during the zero code.
Bit 20 (forth output bit) is the extended input range (EXR)
indicator. If the input is within the normal input range
0␣ ≤␣V
IN
≤ V
REF
, this bit is LOW. If the input is outside the
normal input range, V
IN
> V
REF
or V
IN
< 0, this bit is HIGH.
The function of these bits is summarized in Table 1.
Table 1. LTC2424/LTC2428 Status Bits
Bit 23 Bit 22 Bit 21 Bit 20
Input Range EOC DMY SIG EXR
V
IN
> V
REF
0 011
0 < V
IN
≤ V
REF
0 010
V
IN
= 0
+
/0
–
0 0 1/0 0
V
IN
< 0 0 001
Bit 19 (fifth output bit) is the most significant bit (MSB).
Bits 19-0 are the 20-bit conversion result MSB first.
Bit 0 is the least significant bit (LSB).
Data is shifted out of the SDO pin under control of the serial
clock (SCK), see Figure 4. Whenever CSADC is HIGH, SDO
remains high impedance and any SCK clock pulses are
ignored by the internal data out shift register.
In order to shift the conversion result out of the device,
CSADC must first be driven LOW. EOC is seen at the SDO
pin of the device once CSADC is pulled LOW. EOC changes
real time from HIGH to LOW at the completion of a
conversion. This signal may be used as an interrupt for an
external microcontroller. Bit 23 (EOC) can be captured on
the first rising edge of SCK. Bit 22 is shifted out of the
device on the first falling edge of SCK. The final data bit (Bit
0) is shifted out on the falling edge of the 23rd SCK and
may be latched on the rising edge of the 24th SCK pulse.
On the falling edge of the 24th SCK pulse, SDO goes HIGH
indicating a new conversion cycle has been initiated. This
bit serves as EOC (Bit 23) for the next conversion cycle.
Table 2 summarizes the output data format.
CSADC
SCK
SDO
CONVERSION SLEEP
8 8 8 8 (OPTIONAL)
EOC = 1
EOC = 1
LAST 8 BITS LOGIC
EOC = 0
DATA OUT
4 STATUS BITS 20 DATA BITS
DATA OUTPUT
24248 F03
CONVERSION
Figure 3. LTC2424/LTC2428 Compatible Timing with the LTC2404/LTC2408
(1 paginas)
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